dear dale,
thanks for your answer - i was surprised at how sophisticated the
analysis was, my students have enjoyed the debate,
cheers,
adnan
---
Dale Morris wrote:
> <adnan.aziz@[EMAIL PROTECTED]
> wrote in message
> news:1131558407.194222.326600@[EMAIL PROTECTED]
> >i was curious as to why TLBs are implemented using CAMs.
> >
> > specifically, it seems to me that the organization used in caches
> > (e.g., 4-way set associative) would work as well for a TLB as for a
> > D-cache - you can make much larger SRAMs than CAMs
>
> One reason is variable page sizes (for architectures that sup****t them).
> Caches typically have a fixed line size, and so the division between
index
> and tag for a set-associative cache can be done independent of the data
> being accessed. But, for TLBs that can hold different page sizes, no
static
> division of address bits between index and tag gives you the optimal
design
> (where a mapping for a large page appears just once in the TLB, saving
much
> space over having multiple, smaller mappings).
>
> You could do something like sectoring (as is done in caches), but this
> doesn't give you much dynamic range, and it would mostly defeat the
purpose
> of using only a single TLB entry to map a large address range.
>
> With a CAM implementation of a TLB, each entry holds the virtual page
number
> (which may be variable in the number of bits) and the page size, which
> informs the entry-local match logic as to how many of the incoming VA
bits
> need to match in order to signal a hit for this entry.
>
> > ps - i teach a CMOS vlsi design class at UT Austin, and we're covering
> > RAMs, which led to this question
>
> If you need a concrete example of an architecture with variable page
sizes,
> might I suggest Itanium ;-)
>
> Hope this was helpful to you.
>
> - Dale Morris
> Itanium Processor Architect
> Hewlett-Packard Co.
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