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Computer Aided Design - CAD > LSI circuit testing > tap reset seque...
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tap reset sequence

by "gomsi" <gautamsharma24@[EMAIL PROTECTED] > Dec 18, 2006 at 11:16 PM

I have a simple doubt about resetting sequence of Tap state machine
One way of resetting TAP FSM is through trst signal. Making trst
1(along with TMS=1 for the time trst transitions from 0 to 1) resets
the state machine and it enter run-test-idle mode.

A other way is by asserting TMS=1 for five TCK.. But am not able to do
it this way.. Any clues where i may be going wrong? What should be the
value on other test signals at this time? Since in my case the TAP
remains in test-logic-reset state
 




 2 Posts in Topic:
tap reset sequence
"gomsi" <gau  2006-12-18 23:16:19 
Re: tap reset sequence
"Alvin Andries"  2006-12-27 08:05:04 

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