Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.
I have a circuit connection like this.
--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|
Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not re****ted to be equivalent, but are
alwayd re****ted simulataneously as possible candidates when one of the
faults are inserted.
Is there some possible solution to this situation?
Thanks,
Fazela
