Re: Need an algorithm for BIST to test stuck at faults in an FPGA
by hamidrezah@[EMAIL PROTECTED]
Apr 29, 2006 at 11:51 AM
FPGAs offer JTAG and boundary scan which you can use to access
internals for design verification purposes (testing the design).
Manufacturing testing of FPGAs (like stuck-at testing) is already
performed on FPGAs when you buy them.
Maybe you need to implement a BIST variant in an FPGA just to
explore/practice, then google LFSR BIST VERILOG.
Good Luck.
HrH
