Re: Need an algorithm for BIST to test stuck at faults in an FPGA
by Martin Thompson <martin.j.thompson@[EMAIL PROTECTED]
>
Apr 27, 2006 at 05:04 PM
"pavan.bvsrc@[EMAIL PROTECTED]
" <pavan.bvsrc@[EMAIL PROTECTED]
> writes:
> Hi,
>
> I need an algorithm or verilog/vhdl code for Built in self test that
> can detect stuck at faults in an FPGA. Please help me in this case
>
Why? FPGAs are already tested when you get them.
You could ask on comp.arch.fpga, but they'll say much the same I
imagine :-)
Cheers,
Martin
--
martin.j.thompson@[EMAIL PROTECTED]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt
