Hello All,
I am using Synopsys Design Compiler to synthesize and Tetramax to
generate test patterns for a benchmark file. DC also inserts a scan
chain in the design. I just wanted to know as to how could I validate
the test patterns generated by Tetramax.
Particularly, I was looking at the STIL pattern format. Is it possible
to just use a simple external verilog simulator and give the PI values,
fill the scan chain and observe the PO values as given in the patterns?
I have a STIL file for the s27 benchmark. Now it has a condition
statement in each of the procedures (load_unload, capture, capture_CLK,
capture_RST) followed by a vector statement (which does a force_pi,
measure_po). In the pattern block, each pattern calls for the
load_unload procedure and then for one of the capture procedures.
So I was kind of confused as to what exact values I should use for the
pi's and the scan cells to get the po values as given in each pattern
statement if I was trying to validate the patterns using an external
verilog simulator.
I would greatly appreciate your help regarding this,
Thanks,
Fazela
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