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Computer Aided Design - CAD > LSI > Re: Logic minim...
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Re: Logic minimization software with LUT6 sup****t?

by dudesinmexico@[EMAIL PROTECTED] Sep 26, 2007 at 04:29 PM

On Sep 26, 3:57 pm, Ray Andraka <r...@[EMAIL PROTECTED]
> wrote:
> dudesinmex...@[EMAIL PROTECTED]
 wrote:
> > On Sep 25, 8:48 pm, Marc Randolph <mr...@[EMAIL PROTECTED]
> wrote:
>
> >>On Sep 25, 4:30 pm, dudesinmex...@[EMAIL PROTECTED]
 wrote:
>
> >>>I am looking for open source software for logic minimization (a la
> >>>espresso) targeted to a lookup table based architecture that can take
advantage
> >>>of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5
> >>>implementation).   Is there such a beast?
>
> >>Howdy,
>
> >>You peaked my curiosity.  Could you explain why you need this?
>
> > Sure. I am working at a Virtex 5 design with *lots* of squarer
> > circuits (Z=A*B with A=B) where the input
> > is a  signed 9 bit value in the [-255,255] range. I am wondering if
> > the LUT6 would give any advantage
> > compared to other implementations. Then, looking at Ray Andraka's page
> > on multipliers I realized that
> > a "Partial product LUT multiplier" looks like a good architecture for
> > the squarer (since A=B the number of LUTs is cut in half), and that
> > the LUT6 probably does not buy you more than a LUT4 since the carry
> > chain limits the number of bits to four per slice.
>
> > -Arrigo
>
> The LUT size isn't related directly to the carry chain pitch.  The 6
> input LUTs (12 per partial product for a 6bit in, 12 bit out LUT) make
> your partial products, and then you add those together with the
> appropriate ****fting for the weighting of the partials to arrive at the
> complete square. For 9 input bits though, you really only need 4 and 5
> input LUTs.  A 6 LUT implementation is still going to have 4 partial
> products, so there is no savings over 4/5 input LUTs.
>
> That said, you could use dual ****t BRAMs as direct look-ups instead and
> get two 9 bit squarers per BRAM (one on each ****t).

Ray, nice to hear from you. Yes, I have considered BRAMs as lookup
tables.
In fact, we noticed that Synplify does something pretty cool: it packs
two multipliers
in a single BRAM18, using one ****t for each multiplier. Of course this
is possible since
they share the same table.
According to the do***entation, one can use a BRAM36 as two BRAM18s,
however
PlanAhead refuses to place a pblock with two BRAM18s on any area with
just one BRAM36.
This could be either a PlanAhead bug or simply that the BRAM36 still
has just two ****ts...
 




 11 Posts in Topic:
Logic minimization software with LUT6 support?
dudesinmexico@[EMAIL PROT  2007-09-25 14:30:10 
Re: Logic minimization software with LUT6 support?
Marc Randolph <mrand@[  2007-09-26 03:48:24 
Re: Logic minimization software with LUT6 support?
"comp.arch.fpga"  2007-09-26 14:24:51 
Re: Logic minimization software with LUT6 support?
dudesinmexico@[EMAIL PROT  2007-09-26 15:20:16 
Re: Logic minimization software with LUT6 support?
hal-usenet@[EMAIL PROTECT  2007-09-26 17:26:24 
Re: Logic minimization software with LUT6 support?
Ray Andraka <ray@[EMAI  2007-09-26 18:57:15 
Re: Logic minimization software with LUT6 support?
dudesinmexico@[EMAIL PROT  2007-09-26 16:29:16 
Re: Logic minimization software with LUT6 support?
Ray Andraka <ray@[EMAI  2007-09-26 19:42:39 
Re: Logic minimization software with LUT6 support?
"John_H" <ne  2007-09-26 16:46:47 
Re: Logic minimization software with LUT6 support?
Ray Andraka <ray@[EMAI  2007-09-26 19:57:08 
Re: Logic minimization software with LUT6 support?
"comp.arch.fpga"  2007-09-27 08:21:28 

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