On Sep 25, 8:48 pm, Marc Randolph <mr...@[EMAIL PROTECTED]
> wrote:
> On Sep 25, 4:30 pm, dudesinmex...@[EMAIL PROTECTED]
wrote:
>
> > I am looking for open source software for logic minimization (a la
> > espresso) targeted to a lookup table based architecture that can take
advantage
> > of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5
> > implementation). Is there such a beast?
>
> Howdy,
>
> You peaked my curiosity. Could you explain why you need this?
Sure. I am working at a Virtex 5 design with *lots* of squarer
circuits (Z=A*B with A=B) where the input
is a signed 9 bit value in the [-255,255] range. I am wondering if
the LUT6 would give any advantage
compared to other implementations. Then, looking at Ray Andraka's page
on multipliers I realized that
a "Partial product LUT multiplier" looks like a good architecture for
the squarer (since A=B the number of LUTs is cut in half), and that
the LUT6 probably does not buy you more than a LUT4 since the carry
chain limits the number of bits to four per slice.
-Arrigo
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