Re: Logic minimization software with LUT6 sup****t?

AFAIK there are not good multi level optimization algorithms that take
mapping effects into account. Instead logic optimization is done
independently of mapping.

Usually, first a technology independent multi level logic optimization
is performed. (Based on transformations, ATPG or implications). There
should be academic implementations
for that around. Most of them quite old.
Afterwards technology mapping is performed. Mapping for LUTs can be
done delay optimal in polynomial time.
(Flow map). For 6-LUT FPGAs it might make sense to combine mapping
with retiming to balance the amount of logic between stages.

There is a paper by Sunil Khatri on optimization for networks of PLAs.
A 6-LUT might be large enough to benefit from that approach. (I doubt
it)

Kolja Sulimma



On 25 Sep., 23:30, dudesinmex...@[EMAIL PROTECTED]
 wrote:
> I am looking for open source software for logic minimization (a la
> espresso)
> targeted to a lookup table based architecture that can take advantage
> of six
> inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5
> implementation).
> Is there such a beast?
>
> thanks much
>
> -Arrigo