Hello,
I'am using SIS to simplify some digital circuits. The problem is that
when I work out a small example of a circuit by hand I end up using
about 50 gates (only inverters, and gates and or gates). When I run SIS
on the same problem using a truth table I end up using 80 gates. When I
estimate my simple by hand design for a larger example using more bits
I end up using maybe 80 gates and SIS want to use 300 gates. If I
calculate a simple bound on my problem I get a logarithmic growth of
gates but with SIS I get an quadratic growth. Something must be really
wrong with how I use SIS. Does anyone have any ideas?
My own idea is that SIS maybe takes propagation time into account and
my simple design has a linear growth in propagation delay but I can't
see that it should cost so much to get lower propagation delay.
