Hi All Verilog users:
I am trying to find some study material to cover the basics of logic
design. Actually I am preparing for an interview. Can anyone of you
point to me some material online or forward me any documents that you
have in some of the topics of logic design i.e.
- Timing issues with a logic delay block sandwiched between two flip
flops etc
- Setup and hold time concepts and formulas
- Metastability etc
- General timing issues and faced in logic design synthesis
Your feedback will be greatly appreciated.
Regards,
Salah
salah.kazi @[EMAIL PROTECTED]
gmail . com
salah.kazi@[EMAIL PROTECTED]
(Salah) Kazi
(416) 716-5634 (Cell), (905) 472-8890 (Home)
Fax: (905) 201-8850, salah.kazi@[EMAIL PROTECTED]
