Hi,
Currently I have a design which has many 32 bit multipliers and 64 bit
adders and the area results are discouraging. The nice thing is that I
have a lot of cycles to implement this algorithm. One solution is to
use a few instantiated MACs and mux all the inputs/outputs over many
cycles. Of course this is a tedious and error-prone process. The
question is if I had a Module Compiler license, can I recode this
Verilog implementation in MC language and get MC to do this for me
automatically. If yes, how difficult would it the conversion be ?
Any suggestions, ideas are welcome.
Thanks.
