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Computer Aided Design - CAD > Logic synthesis > Spare cell inse...
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Spare cell insertion

by Verictor <stehuang@[EMAIL PROTECTED] > Jul 20, 2007 at 03:12 PM

Hi,

Can anyone point out some crucial considerations regarding to spare
cell insertions? Besides spare cell insertion during synthesis and
P&R, is it reasonable to have spare cell inserted in Verilog code?

Thanks,




 1 Posts in Topic:
Spare cell insertion
 Verictor <stehuang@[EM  2007-07-20 15:12:10 

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tan12V112 Wed Aug 20 13:58:06 CDT 2008.