On Jun 17, 7:15 am, Koustav <kousta...@[EMAIL PROTECTED]
> wrote:
> Hello everybody,
>
> I wanted to a transient power analysis on
> designs at cell/gate level. I have synthesized the netlist by cadence
> buildgates. I was wondering if synopsis PrimePower could be used for
> this. I do have the 90nm technology files (.tlf and .def).
>
> Also since synopsis tools accept .lib format for
> technolgy files, is there a way I could convert the .tlf into .lib
> format?
>
> Thanks,
> Koustav
Hi,
Along with doing the parasitic extraction, you will also want to run a
verilog simulator first (such as VCS, or whatever one you use). The
simulator can create a VCD file, which PrimePower uses as input so it
knows when all the switching events occur. With the design, the
parasitics, and the VCD file, you should be able to get PrimePower to
create power waveforms for the whole design and/or for subblocks and
cells you are interested in.
By the way, Synopsys has incor****ated the PrimePower features into
PrimeTime, if you have the PrimeTime PX extension.
thanks,
brandon
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