Re: gate sizing and interconnect delay

Mali <mahalingamv@[EMAIL PROTECTED]
> posted on Tue, 05 Jun 2007 20:22:53 -0700:
     "why do most of the papers ignore interconnect delay when
     optimizing power/delay during gate sizing problem.
     
     is it something we can safely ignore even in circuits < 100 nm."

Hello,

You are insightful. Wires' delays are more significant than gates'
delays for gates whose feature sizes are even as large as
approximately 180 nanometers.

I do not know which papers you were checking. Check papers with the
term "Network on Chip" and you should find papers which contain
mentions of this.

Regards,
Colin Paul Gloster