Hello everybody,
I'm Quang Anh. I'm living in Vietnam, a small and nice country in
South Asian. This is the first time I've posted a topic in this group
for help.
I has been working in a hadware company for about one year.
Now, I'm in charge of designing an interrupt controller (INTC) for a
CPU. This module is expected to work at high speed. Therefore, it's
very hard for such a beginner like me to design. One of my concerns is
how to design a fix-prority arbitration circuit whose specification is
as belows:
1. There are 27 interrupt requests, int_req[26:0]
2. Assume that int_req[0] always has higher priority than int_req[1],
int_req[1] has higher prority than int_req[2], and so
on, ...int_req[26] has lowest priority
3. The circuit must be designed by using only combinational logics to
get quick respone latency
My first idea to design this circuit can be explained by using Verilog
as follows:
input [26:0] int_req; //Request
output [26:0] int_gnt; //Grant
assign int_gnt[0] = int_req[0]; //Always accepted
assign int_gnt[1] = ~int_req[0] & int_req[1];
assing int_gnt[2] = ! (int_req[0] & int_req[1]) & int_req[2];
.......
assign int_gnt[26] = ! (int_req[0] & ... & int_req[25]) & int_req[26];
However, when I synthesized my design, the timing constraint could not
be met due to high speed (high clock frequency).
Anyone who knows how to desing this kind of circuit well, would you
kindly teach me ?
Anyone who knows how to synthize such kind of desing effectively (I'm
using Synopsys tool, Design Compiler to synthesize my desing), would
you kindly teach me ?
In addition, could you please tell me some books or website on
internet where I can learn how to design an arbitration circuit
effectively ?
Thank you very much,
Best regards,
Quang Anh
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