Hi,
When I try to write out a gate level netlist by using
write -f verilog -hier -out mydesign.v
I obtained a VO-4 warning: "assign" or "tran" was used. I check the
netlist, the assignment was used for a reset signal. I wonder how to
remove this warning. It is interesting to see that if I have less
hierarchy, I don't see the warning.
One Solvenet article also reflects this but doesn't address the
solution. The link is here:
https://solvnet.synopsys.com/dow_retrieve/Z-2006.12/socug/socug_3.html
Thanks.
