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Computer Aided Design - CAD > Logic synthesis > [DC] Determine ...
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[DC] Determine parameter in set_input_delay?

by "Davy" <zhushenli@[EMAIL PROTECTED] > Feb 26, 2007 at 12:32 AM

Hi all,

When use set_input_delay/set_output_delay, how to determine the -max/-
min parameter? Is it calculated by hand , calculated by tools, or give
out by some standard specification?

Code:
set_input_delay -max 498  -clock EXTSCL [find ****t ddc_sda_i]
set_input_delay -min 0    -clock EXTSCL [find ****t ddc_sda_i]

set_output_delay -max 498 -clock CLK1MHZ [find ****t ddc_sda_o]
set_output_delay -min 0   -clock CLK1MHZ [find ****t ddc_sda_o]


Best regards,
Davy
 




 2 Posts in Topic:
[DC] Determine parameter in set_input_delay?
"Davy" <zhus  2007-02-26 00:32:42 
Re: [DC] Determine parameter in set_input_delay?
"Alvin Andries"  2007-02-26 23:46:27 

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tan12V112 Sat Jul 5 16:12:49 CDT 2008.