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Computer Aided Design - CAD > Logic synthesis > Ways to check a...
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Ways to check a netlist...

by "stefimkert" <stefimke@[EMAIL PROTECTED] > Feb 13, 2007 at 10:49 PM

I'd like to know how people here do their post synthesis netlist
checks, besides formal and functional verfication.  I have a simle
synopsys "check_design" run after doing scan routing and perform a
range of grep's to see if there are 'b0/'b1-s in the netlist, or
assign statements and that kind of not-so-nice stuff.

Do you have more fancy (but free) ways to check?
 




 1 Posts in Topic:
Ways to check a netlist...
"stefimkert" &l  2007-02-13 22:49:49 

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