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Computer Aided Design - CAD > Logic synthesis > Re: DC timing v...
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Re: DC timing violation, what to do first?

by "Thomas Stanka" <usenet_10@[EMAIL PROTECTED] > Jan 5, 2007 at 12:04 AM

Hi,

Davy schrieb:
> I am new to Synopsys DC. And I have a basic problem. When I find timing
> violation in DC re****t, what shall I do first?
>
> 1. Shall I change the script of DC? To let the tools do something like
> retiming?
> 2. Shall I change the RTL code? To pipeline the comb logic manually?
> 3. Other choice, please recommend.

I guess you are new to synthesis, too.
First don't worry, synopsys dc doesn't know your timing, it estimates
your timing. The real timing is available after layout.
If Synopsys DC estimates you have a little slack, I would try to go
ahead. Else you need more detailed changes of the RTL-code.

If you like to meet timing during synthesis, you need to learn
something about how synopsys estimates if you meet timing or not (See
do***entation for a first step).

bye Thomas
 




 10 Posts in Topic:
DC timing violation, what to do first?
"Davy" <zhus  2007-01-03 23:51:08 
Re: DC timing violation, what to do first?
Jerome <jeje@[EMAIL PR  2007-01-04 10:42:13 
Re: DC timing violation, what to do first?
Kim Enkovaara <kim.enk  2007-01-04 13:08:18 
Re: DC timing violation, what to do first?
"Davy" <zhus  2007-01-04 03:22:54 
Re: DC timing violation, what to do first?
"Mike Lewis" &l  2007-01-04 16:50:00 
Re: DC timing violation, what to do first?
nico@[EMAIL PROTECTED] (  2007-01-04 22:53:21 
Re: DC timing violation, what to do first?
"Davy" <zhus  2007-01-04 18:56:00 
Re: DC timing violation, what to do first?
"Mike Lewis" &l  2007-01-05 12:58:53 
Re: DC timing violation, what to do first?
"Thomas Stanka"  2007-01-05 00:04:59 
Re: DC timing violation, what to do first?
Jim Lewis <jim@[EMAIL   2007-01-05 12:48:55 

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tan12V112 Wed Oct 15 15:03:35 CDT 2008.