A false path is not a real path ... the tool does not know what are real
paths and what are not .. it just re****ts the longest path.
A multi-cycle path is a path than can take more than one clock. The design
may be such that a signal is not going to be used for a few clocks after
it
comes out of a FF. You can then tell the tool that this signal has more
time
to propagate using a multi-cycle constraint.
Mike
"Davy" <zhushenli@[EMAIL PROTECTED]
> wrote in message
news:1167909771.705282.273860@[EMAIL PROTECTED]
Jerome,
Thanks a lot!
Can you tell me what's false path and multicycle path mean?
Best regards,
Shenli
Jerome wrote:
> Hi,
>
> i will just describe what i do:
>
> First, try to understand the violation:
> is this a real one?
> if not, add either a false path or a multicycle path or redefine
> the timing definition in order to remove this false violation
> if yes, change the RTL
> regards.
>
>
> Davy a écrit :
> > Hi all,
> >
> > I am new to Synopsys DC. And I have a basic problem. When I find
timing
> > violation in DC re****t, what shall I do first?
> >
> > 1. Shall I change the script of DC? To let the tools do something like
> > retiming?
> > 2. Shall I change the RTL code? To pipeline the comb logic manually?
> > 3. Other choice, please recommend.
> >
> > What cir***stance to do "1" or "2" or "1 and 2 at the same time"?
> >
> > Best regards,
> > Shenli
> >
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