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Computer Aided Design - CAD > Logic synthesis > Re: DC timing v...
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Re: DC timing violation, what to do first?

by Jerome <jeje@[EMAIL PROTECTED] > Jan 4, 2007 at 10:42 AM

Hi,

i will just describe what i do:

First, try to understand the violation:
  is this a real one?
    	if not, add either a false path or a multicycle path or redefine
the timing definition in order to remove this false violation
	if yes, change the RTL
regards.


Davy a écrit :
> Hi all,
> 
> I am new to Synopsys DC. And I have a basic problem. When I find timing
> violation in DC re****t, what shall I do first?
> 
> 1. Shall I change the script of DC? To let the tools do something like
> retiming?
> 2. Shall I change the RTL code? To pipeline the comb logic manually?
> 3. Other choice, please recommend.
> 
> What cir***stance to do "1" or "2" or "1 and 2 at the same time"?
> 
> Best regards,
> Shenli
>
 




 10 Posts in Topic:
DC timing violation, what to do first?
"Davy" <zhus  2007-01-03 23:51:08 
Re: DC timing violation, what to do first?
Jerome <jeje@[EMAIL PR  2007-01-04 10:42:13 
Re: DC timing violation, what to do first?
Kim Enkovaara <kim.enk  2007-01-04 13:08:18 
Re: DC timing violation, what to do first?
"Davy" <zhus  2007-01-04 03:22:54 
Re: DC timing violation, what to do first?
"Mike Lewis" &l  2007-01-04 16:50:00 
Re: DC timing violation, what to do first?
nico@[EMAIL PROTECTED] (  2007-01-04 22:53:21 
Re: DC timing violation, what to do first?
"Davy" <zhus  2007-01-04 18:56:00 
Re: DC timing violation, what to do first?
"Mike Lewis" &l  2007-01-05 12:58:53 
Re: DC timing violation, what to do first?
"Thomas Stanka"  2007-01-05 00:04:59 
Re: DC timing violation, what to do first?
Jim Lewis <jim@[EMAIL   2007-01-05 12:48:55 

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