Hi,
i will just describe what i do:
First, try to understand the violation:
is this a real one?
if not, add either a false path or a multicycle path or redefine
the timing definition in order to remove this false violation
if yes, change the RTL
regards.
Davy a écrit :
> Hi all,
>
> I am new to Synopsys DC. And I have a basic problem. When I find timing
> violation in DC re****t, what shall I do first?
>
> 1. Shall I change the script of DC? To let the tools do something like
> retiming?
> 2. Shall I change the RTL code? To pipeline the comb logic manually?
> 3. Other choice, please recommend.
>
> What cir***stance to do "1" or "2" or "1 and 2 at the same time"?
>
> Best regards,
> Shenli
>


|