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Computer Aided Design - CAD > Logic synthesis > error help
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error help

by "highbluff" <anandsrg@[EMAIL PROTECTED] > Nov 5, 2006 at 06:33 PM

I have a clock constraint which goes like this.

create_generated_clock -name aclk -source [get_****ts {bclk}] -divide_by
32 -duty_cycle 96 [get_****ts {aclk}]

The Design compiler spits out an error message, which looks like this.
Error: Cannot specify -duty_cycle without -multiply_by. (UID-253)

Can someone please help.
 




 3 Posts in Topic:
error help
"highbluff" <  2006-11-05 18:33:04 
Re: error help
"michaelst@[EMAIL PR  2006-11-06 00:41:22 
Re: error help
paulzimmer@[EMAIL PROTECT  2006-11-14 16:38:34 

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tan12V112 Mon Dec 1 10:47:14 CST 2008.