Hi,
This is my first post to this group so let me introduce myself. I am a
new Digital IC Design engineer ( < 1yr experience) currently working on
130nm technology.
I am using the entire Synopsys tool chain from front-to-back end with
Artisan Standard cell library. I have no end of trouble with Artisan
cells and would like to hear from any of you who have also had
problems. Perhaps we can share workarounds that we have stumbled
across.
Tim
