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Computer Aided Design - CAD > Logic synthesis > Re: generated c...
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Re: generated clocks

by "KJ" <kkjennings@[EMAIL PROTECTED] > Sep 2, 2006 at 07:38 PM

"vic marks" <rajan100000@[EMAIL PROTECTED]
> wrote in message 
news:63881$44f9bf51$50392791$26622@[EMAIL PROTECTED]
> Hi,
>
> I need a suggestion in handling the generated clocks for synthesis, and 
> DFT.
> What kind of constraints would be used for generated-clocks during
> synthesis, and DFT design.
>
Same constraints as with any other clock signal; namely, setup time and
hold 
time for inputs, clock to output for outputs

KJ
 




 3 Posts in Topic:
generated clocks
"vic marks" <  2006-09-02 19:28:48 
Re: generated clocks
"KJ" <kkjenn  2006-09-02 19:38:28 
Re: generated clocks
"arant" <ara  2006-09-03 01:34:49 

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tan12V112 Mon Dec 1 9:54:37 CST 2008.