Re: Single bit wires instead of [0:0] busses?

"stefimkert" <stefimke@[EMAIL PROTECTED]
> wrote in message
news:1153728439.979995.253450@[EMAIL PROTECTED]
> How can I prevent the getting single bit busses as [0:0] in my verilog
> netlist? I want just "wires" (std_logic's instead of
> std_logic_vectors):
>
> module lpesram(clk, d, q);
> input  clk;
> input  [0:0] d;
> output [0:0] q;
> wire [0:0] d;
> wire [0:0] q;
>
>     ...
> endmodule
>
>
> PS: I'm using DC 2005.09
>

What's in the source code? std_logic_vector(0 [down]to 0) would result
into
the [0:0] that you see.

Regards,
Alvin.