How can I prevent the getting single bit busses as [0:0] in my verilog
netlist? I want just "wires" (std_logic's instead of
std_logic_vectors):
module lpesram(clk, d, q);
input clk;
input [0:0] d;
output [0:0] q;
wire [0:0] d;
wire [0:0] q;
...
endmodule
PS: I'm using DC 2005.09
