Re: Design Compiler: Output mux for testing fails timing.
by rafeng@[EMAIL PROTECTED]
Jul 10, 2006 at 08:55 AM
michaelst@[EMAIL PROTECTED]
wrote:
> Probably following command will help you:
> set_case_analysis 0 TEST
One more question: Can I set constraints for both cases using this
set_case_analysis or a varient of it? For example if TEST==0 then clkIn
= 1GHz, if TEST==1 then clkIn = 1MHz and put that in the syntheis
constraints?
