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Computer Aided Design - CAD > Logic synthesis > create_generate...
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create_generated_clock (syntax, do I need it?)

by rafeng@[EMAIL PROTECTED] Jul 8, 2006 at 12:32 PM

Hi

I'm having an issue with create_generated_clock in design compiler. I
have a fast clock which I 1) invert and clock flops, 2) divide down and
use to clock more flops.

1) I invert the clock just by "assign clkInNot = ~clkIn;" inside a
module callded clkInv.

Q: Do I need to tell DC this is a clock or will it know?



2) I divide the clock inside a module called clkdiv:

clkdiv clkdiv_inst (
   .clk_in(clk),
   .clk_out(clk_divided),
);

and use the output to clock more flops. The create_generated_clock
statement looks like this:

create_generated_clock -name "DIV4_CLK" -divide_by 4 -source [get_****t
"clk"]  [get_pins "clkdiv/clk_out"]

However this clock does not appear in my clock re****t statements. Do I
have the syntax wrong? 


Thanks.
 




 2 Posts in Topic:
create_generated_clock (syntax, do I need it?)
rafeng@[EMAIL PROTECTED]   2006-07-08 12:32:59 
Re: create_generated_clock (syntax, do I need it?)
"are.aarseth@[EMAIL   2006-07-31 15:38:28 

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tan12V112 Mon Dec 1 8:28:43 CST 2008.