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Computer Aided Design - CAD > Logic synthesis > [synopsys] stru...
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[synopsys] struggling

by "stefimke" <stefimke@[EMAIL PROTECTED] > Jun 19, 2006 at 04:24 AM

I'm fighting with variable substitution in Synopsys DC-shell in tcl/xg
mode.

This is what I want to do:

#-----------------------------------------------------------------------------
# Setting FALSE paths for asynchronous interfacing between clock
domains
#-----------------------------------------------------------------------------
foreach_in_collection clk1 ${clk_lst} {
  foreach_in_collection clk2 ${clk_lst} {
     if { ${clk1} != ${clk2} } {
         echo "Information: Setting false path from ${clk1} to ${clk2}"
         query_objects ${clk1}
         query_objects ${clk2}
         set_false_path -from ${clk1} -to ${clk2}
     }
  }
}


This an output that is printed:

Information: Setting false path from _sel54 to _sel55
{abc_clk}
{abc_clk}

Completely wrong... I don't want to define false paths from flipflops
in the same clock domain.
So the "if" is already going wrong.... does it compare the "_sel54"
with the "_sel55" string?

Anybody?
 




 4 Posts in Topic:
[synopsys] struggling
"stefimke" <  2006-06-19 04:24:41 
Re: struggling
"Aditya Ramachandran  2006-06-20 06:16:08 
Re: struggling
"Aditya Ramachandran  2006-06-20 06:18:05 
Re: struggling
"stefimke" <  2006-06-20 23:01:54 

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