Hi All,
I am trying to use the ITC'99 benchmarks for a project. However these
are supplied only in VHDL/EDIF/BENCH formats. I was in need of the
verilog format. So I used the Synopsys Design Compiler to synthesize
the behavioural VHDL into structural Verilog. However for bigger
designs, DC automatically instantiates DesignWare Library components
like adders, comparators, etc. I was wondering if there was a way to
override this during compilation to get a flat verilog netlist type of
design as the ISCAS89 benchmarks. I also need to insert scan chains for
testing.
I would greatly appreciate if anyone could suggest how I could work
this problem out.
Thanks,
Fazela
