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Latest 200 Posts:
| Post Title | Post by | Date |
| LinkedIn Group for FPGA & CPLD | Vikash <vikashrun... | Jun 23, 2008 at 11:52 AM |
| Primetime: Path Coordinate Information | hamidrezah@[EMAIL PR... | Jun 16, 2008 at 10:06 AM |
| www.e-bayshoe.com wholesale jordan air max 90 95 l... | ebayshoe1@[EMAIL PRO... | May 13, 2008 at 08:23 AM |
| Re: Breaking News ... Accellera Verification Worki... | Dave Rich <dave.n... | May 12, 2008 at 10:04 AM |
| Re: Breaking News ... Accellera Verification Worki... | harrytheasicguy@[EMA... | May 11, 2008 at 01:18 AM |
| FAST EASY MONEY | "jburgess"... | May 8, 2008 at 03:35 PM |
| Re: Breaking News ... Accellera Verification Worki... | BestInSoC@[EMAIL PRO... | Apr 25, 2008 at 04:20 PM |
| Re: Breaking News ... Accellera Verification Worki... | Jason Zheng <Xin.... | Apr 25, 2008 at 11:05 AM |
| Re: Breaking News ... Accellera Verification Worki... | BestInSoC@[EMAIL PRO... | Apr 25, 2008 at 10:48 AM |
| Breaking News ... Accellera Verification Working G... | HairyTheASICGuy@[EMA... | Apr 25, 2008 at 10:35 AM |
| 2nd CFP - The 1st International Workshop on Bit-Pr... | "bit.precise.re... | Apr 6, 2008 at 10:21 PM |
| forte escape mp3 joseph forte basketball forte dan... | fakepbell@[EMAIL PRO... | Mar 27, 2008 at 05:44 AM |
| gail mckenna topless pics jacqueline bisset toples... | elder0pics@[EMAIL PR... | Mar 24, 2008 at 07:23 AM |
| FPGA/CPLD group on LinkedIn | wmwmurray@[EMAIL PRO... | Mar 7, 2008 at 02:26 AM |
| 2nd CFP: DATICS 2008 - Design, Analysis and Tools ... | DATICS2008 <ss.da... | Mar 5, 2008 at 04:10 PM |
| Think Silicon announces IP Partnership programme | Iakovos Stamoulis &l... | Feb 28, 2008 at 02:50 PM |
| CFP: DTVCS 2008 - Design, Testing and Formal Verif... | "dtvcs2008"... | Feb 15, 2008 at 04:07 PM |
| Persia Asynchronous Synthesis Tool | "mehrdad.najibi... | Feb 5, 2008 at 07:10 AM |
| writing dc_shell output | mmb9305 <michelle... | Jan 29, 2008 at 08:36 AM |
| CFP: DATICS 2008 - Design, Analysis and Tools for ... | ss.datics@[EMAIL PRO... | Jan 23, 2008 at 02:10 PM |
| Scholarships for PhD study in Informatics@Edinburg... | Don Sannella <D.T... | Dec 31, 2007 at 03:20 PM |
| [Chip-Level synthesis] I/O synthesis constraints | Dmitry.Leyzerovich@[... | Dec 18, 2007 at 10:03 PM |
| Registrations open for VLSI Conference 2008 in Hyd... | gdbansal@[EMAIL PROT... | Nov 22, 2007 at 07:38 PM |
| Re: TSMC 90nm library spice deck | Colin Paul Gloster &... | Nov 15, 2007 at 01:07 PM |
| engineering software special offer | "CAD Engineerin... | Nov 8, 2007 at 01:36 PM |
| TSMC 90nm library spice deck | Koustav <koustav7... | Nov 5, 2007 at 08:34 AM |
| Final call for papers - ISQED08 | "SVTI" <... | Oct 28, 2007 at 11:25 AM |
| Think Silicon introduces IPGenius: The first on-li... | Iakovos Stamoulis &l... | Oct 19, 2007 at 12:34 PM |
| IEEE ISQED08 FINAL CALL FOR PAPERS | "SVTI" <... | Oct 16, 2007 at 10:26 AM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 20, 2007 at 06:26 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 20, 2007 at 06:06 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 20, 2007 at 06:02 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Shannon <sgomes@[... | Sep 20, 2007 at 07:48 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | "FreeRTOS.org&q... | Sep 20, 2007 at 07:13 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 20, 2007 at 11:53 AM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 18, 2007 at 03:05 PM |
| Gate level tool for Soft error rate estimate | Koustav <koustav7... | Sep 18, 2007 at 09:24 AM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Evan Lavelle <nos... | Sep 18, 2007 at 01:22 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 17, 2007 at 05:22 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 17, 2007 at 04:55 PM |
| Re: SPAM for vaporware (was: YARDstick - custom pr... | Uncle Noah <nkavv... | Sep 17, 2007 at 04:51 PM |
| SPAM for vaporware (was: YARDstick - custom proces... | JeffM <jeffm_@[EM... | Sep 17, 2007 at 09:41 AM |
| [ANNOUNCE] YARDstick - custom processor developmen... | Uncle Noah <nkavv... | Sep 17, 2007 at 05:35 AM |
| Re: RTL Synthesis & SDF file | Koustav <koustav7... | Sep 13, 2007 at 08:04 AM |
| ISQED08 Call for Papers | "ISQED" &l... | Sep 9, 2007 at 02:25 PM |
| ISQED08 Call for Papers | "ISQED" &l... | Sep 9, 2007 at 02:24 PM |
| Re: Question on .slib file extension | SB <smartbadge@[E... | Sep 6, 2007 at 01:08 AM |
| CfP: EvoHOT 2008 | "squillero@[EMA... | Sep 5, 2007 at 01:38 AM |
| Re: Question on .slib file extension | "Alvin Andries&... | Sep 4, 2007 at 10:22 PM |
| Question on .slib file extension | SB <smartbadge@[E... | Sep 4, 2007 at 10:40 AM |
| RTL Synthesis & SDF file | "asic1234@[EMAI... | Aug 29, 2007 at 09:01 PM |
| Re: plib format | "Alvin Andries&... | Aug 26, 2007 at 11:09 PM |
| .plib library format description | SS <sriram.sambam... | Aug 26, 2007 at 12:38 AM |
| plib format | SS <sriram.sambam... | Aug 26, 2007 at 12:34 AM |
| Gana Dinero Suuuuper Rápido "Earn Money Very ... | "Rutmy" &l... | Aug 17, 2007 at 01:46 PM |
| Exciting openings for Standard Cell libraries/Memo... | Nitin Gupta <niti... | Aug 6, 2007 at 07:53 AM |
| Re: A useful CPF (Common Power Format) website | grgburdell@[EMAIL PR... | Aug 3, 2007 at 08:26 PM |
| Re: Automatic Schematic Generation (System Graph) ... | krw <krw@[EMAIL P... | Jul 23, 2007 at 09:06 AM |
| Spare cell insertion | Verictor <stehuan... | Jul 20, 2007 at 03:12 PM |
| Re: SynaptiCAD AllProducts, Synopsys, new programs... | Jogi <joginder.si... | Jul 20, 2007 at 11:52 AM |
| SynaptiCAD AllProducts, Synopsys, new programs, | ola7 <springsingr... | Jul 19, 2007 at 01:07 AM |
| A useful CPF (Common Power Format) website | grgburdell@[EMAIL PR... | Jul 11, 2007 at 09:19 AM |
| World-Premiere of EMPIRE 2D | "EMPIRE2D"... | Jun 23, 2007 at 11:26 AM |
| VHDL and Verilog - 15 x Contract Engineers Require... | Specialist Verilog E... | Jun 27, 2007 at 06:35 AM |
| Re: gate sizing and interconnect delay | "mahalingamv@[E... | Jun 26, 2007 at 02:13 AM |
| Re: PrimePower | "Alvin Andries&... | Jun 20, 2007 at 01:31 AM |
| Re: PrimePower | Koustav <koustav7... | Jun 19, 2007 at 02:39 PM |
| Re: PrimePower | brandon thompson <... | Jun 19, 2007 at 03:20 PM |
| Re: PrimePower | "Alvin Andries&... | Jun 18, 2007 at 10:42 PM |
| PrimePower | Koustav <koustav7... | Jun 17, 2007 at 02:15 PM |
| Re: gate sizing and interconnect delay | Colin Paul Gloster &... | Jun 12, 2007 at 11:48 AM |
| gate sizing and interconnect delay | "mahalingamv@[E... | Jun 5, 2007 at 08:22 PM |
| Mind Control and Directed Energy Weapons | soleilmavis <sole... | May 15, 2007 at 05:23 PM |
| How to design and synthesize an abitration cicuit ... | Quang Anh <nvqanh... | Apr 27, 2007 at 07:06 AM |
| ANN: Tyd-IP Code Generator V3.1 released | "Mike" <... | Apr 19, 2007 at 09:47 AM |
| Scripting best practicies | "cafm" <... | Apr 16, 2007 at 10:39 AM |
| EDP 2007 (Power and DFM Focus) -- Early Registrati... | b_kapoor@[EMAIL PROT... | Mar 30, 2007 at 08:19 AM |
| GUI for SIS | Michele Russo <ru... | Mar 16, 2007 at 07:50 PM |
| Nice VLSI Site | pro.vlsi@[EMAIL PROT... | Mar 12, 2007 at 08:35 AM |
| VO-4 warnings when wrapping modules | "Verictor"... | Mar 6, 2007 at 04:27 PM |
| A very good website for VLSI chip Designers | "chipdesignart&... | Mar 5, 2007 at 11:38 PM |
| .db to .lib synopsys | vishalps@[EMAIL PROT... | Mar 5, 2007 at 09:31 AM |
| =?windows-1256?B?KCgg1dzc3Nzm0SApKSAgxe3Rx+TtIO3d2... | "=?windows-1256... | Mar 5, 2007 at 03:51 AM |
| Re: [DC] Determine parameter in set_input_delay? | "Alvin Andries&... | Feb 26, 2007 at 11:46 PM |
| [DC] Determine parameter in set_input_delay? | "Davy" <... | Feb 26, 2007 at 12:32 AM |
| Re: a problem when using dc_shell-t>report_lib | "Alvin Andries&... | Feb 25, 2007 at 11:02 PM |
| a problem when using dc_shell-t>report_lib | "hurricane"... | Feb 21, 2007 at 08:47 AM |
| netlist viewer? | "Tony T" &... | Feb 17, 2007 at 05:31 PM |
| netlist viewer? | "Tony T" &... | Feb 17, 2007 at 05:30 PM |
| Ways to check a netlist... | "stefimkert&quo... | Feb 13, 2007 at 10:49 PM |
| "assign" warnings after synthesis | "Verictor"... | Feb 12, 2007 at 04:04 PM |
| Top-bottom Synthesis methodology Paper from SNUG? | "Davy" <... | Feb 5, 2007 at 01:38 AM |
| OPT314: disabling timing arc between pins | "Verictor"... | Feb 1, 2007 at 12:38 PM |
| Re: Datapath design problem? | Ray Andraka <ray@... | Jan 28, 2007 at 05:37 PM |
| Datapath design problem? | "Shenli" &... | Jan 25, 2007 at 10:37 PM |
| Autochar by Robert Yu is available with me | "KR" <k... | Jan 24, 2007 at 09:36 AM |
| CFP: CEC2007 Special session on: Evolutionary Comp... | squillero@[EMAIL PRO... | Jan 24, 2007 at 01:12 AM |
| Constraining Multiple clock design | umrtech@[EMAIL PROTE... | Jan 15, 2007 at 10:13 PM |
| Re: Use Multi-cycle Path or Pipeline? | Mike Treseler <mi... | Jan 8, 2007 at 07:30 AM |
| Re: Use Multi-cycle Path or Pipeline? | Jerome <jeje@[EMA... | Jan 8, 2007 at 01:41 PM |
| Re: Use Multi-cycle Path or Pipeline? | "Hans" <... | Jan 8, 2007 at 09:56 AM |
| Re: Use Multi-cycle Path or Pipeline? | kayrock66@[EMAIL PRO... | Jan 7, 2007 at 09:45 PM |
| Re: Use Multi-cycle Path or Pipeline? | Mike Treseler <mi... | Jan 7, 2007 at 09:45 PM |
| Use Multi-cycle Path or Pipeline? | "Davy" <... | Jan 7, 2007 at 06:08 PM |
| Re: DC timing violation, what to do first? | Jim Lewis <jim@[E... | Jan 5, 2007 at 12:48 PM |
| Re: DC timing violation, what to do first? | "Mike Lewis&quo... | Jan 5, 2007 at 12:58 PM |
| Re: DC timing violation, what to do first? | "Thomas Stanka&... | Jan 5, 2007 at 12:04 AM |
| Re: DC timing violation, what to do first? | "Davy" <... | Jan 4, 2007 at 06:56 PM |
| Re: DC timing violation, what to do first? | nico@[EMAIL PROTECTE... | Jan 4, 2007 at 10:53 PM |
| Re: DC timing violation, what to do first? | "Mike Lewis&quo... | Jan 4, 2007 at 04:50 PM |
| Re: DC timing violation, what to do first? | "Davy" <... | Jan 4, 2007 at 03:22 AM |
| Re: DC timing violation, what to do first? | Kim Enkovaara <ki... | Jan 4, 2007 at 01:08 PM |
| Re: DC timing violation, what to do first? | Jerome <jeje@[EMA... | Jan 4, 2007 at 10:42 AM |
| DC timing violation, what to do first? | "Davy" <... | Jan 3, 2007 at 11:51 PM |
| help me | "salu" <... | Dec 30, 2006 at 11:15 PM |
| Re: Should I use an external synthesis tool? | "Gupta" &l... | Dec 30, 2006 at 12:44 AM |
| Find wires optimized away by synthesis in netlist | nandigits@[EMAIL PRO... | Dec 28, 2006 at 11:58 AM |
| Studentships for PhD study in Informatics@Edinburg... | Don Sannella <D.T... | Dec 22, 2006 at 03:47 PM |
| Query :Regarding Synthesis Report | "kartheic anan... | Dec 8, 2006 at 11:41 AM |
| =?iso-8859-15?Q?=D5=DB=BF=DB?= | feda@[EMAIL PROTECTE... | Nov 24, 2006 at 07:54 AM |
| Graph Data structure to storing components in spic... | "Jonay Aloat&qu... | Nov 23, 2006 at 06:13 PM |
| Re: error help | paulzimmer@[EMAIL PR... | Nov 14, 2006 at 04:38 PM |
| Re: creating a .lib file ? | pengdaimin@[EMAIL PR... | Nov 9, 2006 at 10:31 AM |
| Should I use an external synthesis tool? | "avishay" ... | Nov 6, 2006 at 08:15 AM |
| Re: error help | "michaelst@[EMA... | Nov 6, 2006 at 12:41 AM |
| error help | "highbluff"... | Nov 5, 2006 at 06:33 PM |
| CFP: EvoHOT 2007 | squillero@[EMAIL PRO... | Sep 28, 2006 at 10:49 AM |
| FREE ARTICLES PUBLISHING SERVICE | "smart" &l... | Sep 24, 2006 at 09:14 AM |
| Artisan Cell Libraries in Synopsys Design Flow | "Tim" <... | Sep 19, 2006 at 11:30 PM |
| Re: generated clocks | "arant" &l... | Sep 3, 2006 at 01:34 AM |
| Re: generated clocks | "KJ" <k... | Sep 2, 2006 at 07:38 PM |
| generated clocks | "vic marks"... | Sep 2, 2006 at 07:28 PM |
| Re: Calculate Delay from .Lib file | mk <kal*@[EMAIL P... | Aug 30, 2006 at 04:17 AM |
| Encounter RTL libraries | "michael_skoufi... | Aug 29, 2006 at 12:05 PM |
| Calculate Delay from .Lib file | "Ali Arabi"... | Aug 28, 2006 at 04:46 PM |
| Call for Papers - IEEE ISQED07 | "ISQED" &l... | Aug 16, 2006 at 10:38 PM |
| Re: Add money to your Paypal account with OPRAH V'... | "Jogi" <... | Aug 16, 2006 at 02:39 AM |
| Re: create_generated_clock (syntax, do I need it?) | "are.aarseth@[E... | Jul 31, 2006 at 03:38 PM |
| Reflections on good and evil | booktwo@[EMAIL PROTE... | Jul 28, 2006 at 07:57 AM |
| Re: Single bit wires instead of [0:0] busses? | "Alvin Andries&... | Jul 26, 2006 at 07:27 PM |
| Single bit wires instead of [0:0] busses? | "stefimkert&quo... | Jul 24, 2006 at 01:07 AM |
| Re: help me | "sspreddy@[EMAI... | Jul 20, 2006 at 09:15 AM |
| where to find 130 nm 90 nm technology files | "mahalingamv@[E... | Jul 15, 2006 at 02:49 PM |
| Re: help me | "michaelst@[EMA... | Jul 12, 2006 at 12:32 AM |
| help me | "salu" <... | Jul 11, 2006 at 06:36 AM |
| synthesis help me | "salu" <... | Jul 11, 2006 at 03:04 AM |
| Re: Design Compiler: Output mux for testing fails ... | rafeng@[EMAIL PROTEC... | Jul 10, 2006 at 08:55 AM |
| Re: Design Compiler: Output mux for testing fails ... | rafeng@[EMAIL PROTEC... | Jul 9, 2006 at 09:52 AM |
| Re: Design Compiler: Output mux for testing fails ... | mikeotp@[EMAIL PROTE... | Jul 9, 2006 at 03:47 AM |
| Re: Design Compiler: Output mux for testing fails ... | "michaelst@[EMA... | Jul 9, 2006 at 01:38 AM |
| create_generated_clock (syntax, do I need it?) | rafeng@[EMAIL PROTEC... | Jul 8, 2006 at 12:32 PM |
| Design Compiler: Output mux for testing fails timi... | rafeng@[EMAIL PROTEC... | Jul 8, 2006 at 12:13 PM |
| Extract Logic Cone by GOF | nandigits@[EMAIL PRO... | Jul 8, 2006 at 09:49 AM |
| Re: struggling | "stefimke"... | Jun 20, 2006 at 11:01 PM |
| Re: struggling | "Aditya Ramacha... | Jun 20, 2006 at 06:18 AM |
| Re: struggling | "Aditya Ramacha... | Jun 20, 2006 at 06:16 AM |
| Re: Synopsys Tetramax | "michaelst@[EMA... | Jun 20, 2006 at 12:36 AM |
| 2006/June/19 new CAD programs | "T.E.L." &... | Jun 19, 2006 at 10:26 PM |
| Synopsys Tetramax | "Fazela" &... | Jun 19, 2006 at 01:11 PM |
| [synopsys] struggling | "stefimke"... | Jun 19, 2006 at 04:24 AM |
| autochar ? | mk <kal*@[EMAIL P... | Jun 18, 2006 at 02:25 AM |
| Re: Too big load in netlist after DC synthesis | "Aditya Ramacha... | Jun 15, 2006 at 02:36 AM |
| Re: Unsupported verilog construct with synopsys DC... | "michaelst@[EMA... | Jun 15, 2006 at 01:56 AM |
| Re: Too big load in netlist after DC synthesis | "michaelst@[EMA... | Jun 15, 2006 at 01:54 AM |
| Unsupported verilog construct with synopsys DC? | "Fazela" &... | Jun 14, 2006 at 03:30 PM |
| Too big load in netlist after DC synthesis | "gongguowang@[E... | Jun 14, 2006 at 06:51 AM |
| FPGA Glossary from Web Services free | "smart" &l... | Jun 8, 2006 at 05:51 AM |
| Math Solving, and Statistics Programs | loa210@[EMAIL PROTEC... | May 31, 2006 at 10:19 AM |
| EDA, PCB, programs, | loa210@[EMAIL PROTEC... | May 31, 2006 at 10:07 AM |
| Mentor Graphics programs 2006 - | loa210@[EMAIL PROTEC... | May 31, 2006 at 10:06 AM |
| Tornado, VxWorks, Wind River, ARM, ArmCAD, Nationa... | loa210@[EMAIL PROTEC... | May 31, 2006 at 10:05 AM |
| negative hold time | "skyworld"... | May 28, 2006 at 07:00 AM |
| Re: dc_shell and disabling datapath optimization v... | "michaelst@[EMA... | May 21, 2006 at 01:34 AM |
| dc_shell and disabling datapath optimization varia... | "Fazela" &... | May 20, 2006 at 12:37 AM |
| Regarding synthesis of itc99 benchmarks | "Fazela" &... | May 19, 2006 at 08:15 AM |
| Re: set_load & set_fanout_out | "michaelst@[EMA... | May 18, 2006 at 01:38 AM |
| set_load & set_fanout_out | "skyworld"... | May 17, 2006 at 06:38 PM |
| Re: Define clock in Synplicity | g.shrinivasan@[EMAIL... | May 16, 2006 at 06:42 AM |
| Re: Where can I find latency of my circuit in Syno... | "SS" <s... | May 15, 2006 at 05:37 PM |
| Re: Where can I find latency of my circuit in Syno... | "eda_cadence&qu... | May 15, 2006 at 12:58 AM |
| Where can I find latency of my circuit in Synopsys... | "friend.05@[EMA... | May 14, 2006 at 04:16 PM |
| Re: Pros/Cons of skew & latency? | "eda_cadence&qu... | May 11, 2006 at 11:49 PM |
| SPICE netlist parser | Giannis Papadopoulos... | May 9, 2006 at 01:14 AM |
| Re: Verilog book recommendation | "gabor" &l... | Apr 29, 2006 at 01:42 PM |
| Problem of generics with SDF simulation of VHDL de... | "Fazela" &... | Apr 29, 2006 at 06:54 AM |
| Verilog book recommendation | "hdl_book_selle... | Apr 28, 2006 at 07:12 PM |
| Re: synopsys parallel case | Michael Laajanen <... | Apr 27, 2006 at 07:51 PM |
| Re: Pros/Cons of skew & latency? | "SS" <s... | Apr 27, 2006 at 06:39 AM |
| read_saif -scale problem | "SS" <s... | Apr 26, 2006 at 05:41 AM |
| synchr.and asynchr. | "Maryam" &... | Apr 23, 2006 at 08:06 AM |
| Define clock in Synplicity | "Moises" &... | Apr 18, 2006 at 04:40 AM |
| Re: synopsys parallel case | mk<kal*@[EMAIL PR... | Apr 17, 2006 at 02:42 PM |
| Re: synopsys parallel case | "Maryam" &... | Apr 17, 2006 at 02:12 AM |
| Re: synopsys parallel case | "michaelst@[EMA... | Apr 16, 2006 at 12:44 AM |
| synopsys parallel case | "Maryam" &... | Apr 15, 2006 at 09:24 PM |
| synopsys parallel case | "Maryam" &... | Apr 15, 2006 at 09:24 PM |
| Pros/Cons of skew & latency? | "gopal" &l... | Apr 13, 2006 at 04:12 AM |
| Re: design compiler help | "tellankush@[EM... | Apr 12, 2006 at 04:51 PM |
| Re: design compiler help | "michaelst@[EMA... | Apr 12, 2006 at 12:34 AM |
| Re: design compiler help | "mahalingamv@[E... | Apr 11, 2006 at 12:41 PM |
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