Hi Jorge,
Your professor's answer does not surprise me. The number of engineers
I knew who ignore this capability is rather high.
I do agree with St=E9phane's mathematics formulas. The silicon physical
reality could be slightly different though.
The Mismatch data as provided in your model cards are extracted for
well defined structures within well defined limits. Your foundry does
not guaranty any mathematical continuity if your design structure is
different from those used for mismatch data extraction.
BTW, why don't you run few MC simulation with/without correlation to
see what's the impact on your output ? We tend sometimes to argue on
very little tiny things that end up with no impact at all. You can use
a dcmatch analysis if this is possible for you, this will give you a %
of impact. MC simulations are rather time-consuming for big designs.
Please bear in mind that what we do in industry is slightly different
from what we learn in the academia. When we design a chip for mass
production, it is common to make some over-design to ensure that all
the cases are covered, we don't take any chance as we do for R&D
projects. In other words, what is meant to be couple of transistors
for a differential pair in the theory could end up with many
transistors around for any sort of trimming.
I have written few notes about some useful mathematics I did use when
designing LDO voltage regulators. You will find some stats in French :-
(
http://riad-kaced-usenet-group.googlegroups.com/web/appendixB.pdf?gda=3Dudm=
_Gz8AAAACEayrvYwHm6dMlpKZwWtSl5XM8QT5aVY4zRoM1QEH0iZmloksgQP40rJyRdm_P56ccy=
FKn-rNKC-d1pM_IdV0&gsc=3DeBZqKyEAAAAWRXdowyh_lQVwEfXi7GrRp7kbrQuQTkuyp0rhe4=
k7aUzfKN-m9S9niuHrq-IEXAE
But if you don't want to waste plenty of time understanding French for
4 pages of mathematics, then go for any descent 'Mathematics for
Engineers' book as St=E9phane mentioned earlier. I've got one at my
office, I can send you the title/author later on if you want.
Cheers,
Riad.
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