Jorge,
You might find this thread worthy of a look :
http://groups.google.com/group/comp.cad.cadence/tree/browse_frm/thread/4fbe2dbd2ed1afa1
If you take a look at BSIM4 manual for instance, you will see that it's
almost 200 pages in length,
most of it filled with equations. Now you're basically asking how to
reduce these 200 pages to a
single equation, unfortunately it's not possible. And due to the
complexity of the model, there's no
one-to-one correspondence between BSIM parameters and simple
hand-calculation model.
If you really want those numbers, the simplest way is extract the model
yourself by matching it to
simulation results. You should be aware that a simple model will be valid
only for specific
transistor geometries, bias and operating conditions.
Good Luck,
Stéphane
spectrallypure wrote:
>> I would like to remind you that for modern processes due to LDD
>> structures CGD capacitances are voltage dependent, since depletion
>> region capacitance in Lightly Doped areas is voltage dependent.
>
> Really? ...this is getting worse than I thought! :S
> Could you recommend any book or paper where I could learn more about
> how to take into account this at design phase?
> Thanks for the info!
>
> Regards,
> Jorge
>
>
>
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