Hi Jorge,
The last time I was doing propoer IC design work was 5 years back.
At that time, I was rather using the very basic equations you can find
in any descent analog book.
For example, the equation to compute the Drain-bulk capacitance is
given by:
Cdb={(AD*CJ)/(1+Vdb/PB)^MJ)}+{(PD*CJsw)/(1+Vdb/PB)^MJsw)}
Cdb= Area contribution + SideWall contribution.
1. AD and PD are the Area/Perimeter of the drain junction
2. Vdb is the Drain-Bulk voltage
3. CJ, MJ, CJsw, MJsw, PB are process parameters you can get either
from your model card or from any do***ent that is provided by your
foundry:
-> CJ=Zero-bias junction bottom capacitance density.
-> MJ=Bulk junction bottom grading coefficient.
-> CJsw=Zero-bias junction sidewall capacitance density.
-> MJsw=Bulk junction sidewall grading coefficient.
-> PB=Bulk junction built-in potential
You can calculate the Csb the same way.
Give a look at the gate capacitance in any of your books as well.
I'm always taking the very simple equations when it comes to make a
first hand made design. I then play around with the simulation to
tweak the values of each single transistor.
Hope this helps.
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