Hi all!
Despite having reviewing some previous posts about the values re****ted
by Virtuoso for the small-signal parasitic capacitances of transistors
(e.g. see
http://groups.google.com/group/comp.cad.cadence/browse_thread/thread/4fbe2dbd2ed1afa1/e0f324447dc2887f
or Sourcelink Solution Number 1814346), I am still unable to figure
out how to convert these values to others useful for hand
calculations.
For instance, the Sourcelink solution states-among many other
equations-that:
....
cgd = Cgd - Cgdovl
Cgdovl = pInst->pSDModel->OverlapCgd * pInst->MFactor;
....
On the other hand, for a particular simulation I am getting
cgd=-226.9a and cgdovl=166.3a. According to the above equation, then
Cgd = cgd+Cgdovl=-60.6a. So I wonder...
Is this the correct way for obtaining the values of the "physical"
parasitic capacitances of a transistor (Cgd, Cgs, Cdb, Csb, Cgb,
etc.)?
-If no, then... how can they be properly calculated from the values
re****ted by Cadence?
-If yes, ...how should I interpret, for instance, the result
Cgd=-60.6a (negative)? From the formal definition, I guess this means
that the gate charge decreases as the the drain voltage increases...
BUT what capacitance value should be actually drawn in a pencil-and-
paper schematic between the gate and the drain?
Thanks in advance for your help!
Regards,
Jorge.
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