I used both PKS and RTL compiler to synthesize a verilog file, then
used the .v file to do place and route with soc encounter. When I do
post-layout simulation, I find that the routing result file using .v
file generated by PKS produced the right result, while the one
using .v file generated by RTL compiler cannot produce the right
result, because the synthesis result from RTL compiler contained:
assign SelExt = IR[15];
assign SelV0 = SelC0;
assign SelZ0 = SelC0;
assign SelZ = SelC;
assign SelV = SelC;
Then after routing, when I do extraction, there are only SelZ, SelZ0
and SelExt signals left, while SelC, SelC0, SelV and SelV0 are deleted
as being the same nets, so it caused problems of not matching the IO
list of the module when I simulate.
Then I tried with another behavioural design, similarly the routing
result using PKS as synthesis tool produced the right result, while
the one using RTL compiler failed to pass the simulation. But this
time, it did not have the same nets problem, just not being able to
produce the right result.
I don't understand. Is that possible that using PKS and RTL compiler
synthesize the same design while the files did not have the same
function? Or I made mistakes? (I used the same process to do place and
route and except the .v file, the two designs have the same other
files)
Thank you!
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