Pieter,
There are several ways to go about this. Depending on the data you have,
and your LVS tool (in this
regard, as Riad pointed, I believe they have all more or less the same
capabilities and requirements).
Essentially, you need a layout and a schematic...
For the layout, you can typically obtain a complete transistor-level
layout in GDS format directly
from your P&R tool, provided you have the full layouts of your standard
cells available. If it is
not the case, then you'll have to go for a gate-level LVS.
For the schematic... well the P&R tool does not bother with what's inside
the cells, so typically
you can create a gate-level netlist only (in verilog format - cdl, maybe
but I personally do not
like it).
The missing piece here is what's inside the cells (unless you go for
gate-level...). It can be
available in different forms, from your library vendor. It could be SPICE
or CDL netlists. It could
be a CDB/OA library with complete schematics. It could be a textual
schematic such as EDIF.
Now you have to put all this together, and there are several ways to go
about it as well. If you had
schematics for your cells, you may decide to im****t your verilog netlist
into a gate-level
schematic, this way you'd have all the information in schematic form. You
could also im****t the
verilog down to gate level, and include your standard cells netlists in
the LVS run to complete the
information. Or, you could im****t nothing - just a symbol of your digital
block that you'd place in
a schematic ; then you'd need to include your block's gate-level netlist
in addition to the cells
transistor-level netlist into the LVS run.
That last option seems to be your choice. It would be mine too, as I said,
I like to avoid all the
manipulations (such as im****ting the block) which take time at each
turnaround, and may be error
factors.
Now after all this blabbering, I have merely restated your question :) How
do you do it ? Simple :
im****t your verilog netlist into virtuoso with File->Im****t->Verilog. If
you want only a symbol,
just set "Im****t structural modules as functional". If you want a
schematic, set "Im****t structural
modules as schematic" and add your cell library in the "Reference Library"
field, this way it will
use the symbols from that library to build up your schematic. If you don't
have symbols for your
cell library, just create them before by im****ting the behavioral verilog
description of your cells
into a new library to generate the symbols and functional views...
The last part is to properly setup your LVS tool to include the missing
information (verilog netlist
of your digital block + transistor-level netlists of the cells). Here it
depends on the particular
tool ; with assura you'd just add the file in "Netlisting Options". With
calibre, as Riad mentioned,
you'd convert your verilog to a calibre-compliant CDL by using the
command-line tool "v2lvs2" and
include all files in the run.
Feew. Hope it helps now... Cheers.
Stéphane
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