On Aug 25, 8:00=A0am, pdw <dewit.pie...@[EMAIL PROTECTED]
> wrote:
> Hi Riad,
> thanks for your quick response!
>
> This cdl netlist, where can I find this? Is it generated by Encounter?
> Or do I need to ex****t it from Synopsys DC? (As you see, this is the
> first time I do a std cell design...)
>
> What I ideally want, is the Verilog functional view, layout and symbol
> view associated with the same circuit.
>
> Regards,
> Pieter
>
> On Aug 25, 8:53 am, Riad KACED <riad.ka...@[EMAIL PROTECTED]
> wrote:
>
> > On Aug 25, 7:43 am, pdw <dewit.pie...@[EMAIL PROTECTED]
> wrote:
>
> > > Hello,
> > > I have some standard-cell logic I want to add to an analog circuit.
I
> > > generated the standard-cell layout using SoC Encounter and have
> > > im****ted it into Cadence.
>
> > > Is it possible to create a symbol view corresponding to the layout
> > > (according to the Verilog code), so I can add this symbol in my
> > > schematic and run a LVS for the complete system?
>
> > > Thanks a lot,
> > > Pieter
>
> > Ciao Pieter,
>
> > Yes of course it is possible.
> > You just need to include the cdl netlist corresponding to your digital
> > when running your Assura/Calibre LVS. Simple as that ;-)
>
> > Cheers,
> > Riad.
Ciao Pieter,
Both Calibre/Assura can be used for LVS with a gate level Verilog
netlist. You can use that Verilog netlist for your block. The CDL
netlist I'm talking about is the one defining the primitives of the
gates. This CDL netlist should be provided by your PDK/Foundry/
DigitalLib provider.
If you are interested in CDL netlisting:
1. I'm pretty much sure your digital tool is able to ex****t a cdl
netlist. Usually, the digital blocks come with a layout, a structural/
functional HDL and often the CDL netlist. My guess is that digital
tools are able to ex****t CDLs but my knowledge in there (Digital BE)
is very weak I'm afraid :-(
2. If not, then you can im****t your verilog in DFII using Otherwise
you can do this by using CIW->File->Im****t->Verilog. This will make a
schematic of your design and you don't need any CDL netlist for the
LVS in this case. But if you want to make it anyway, you can run CIW-
>File->Ex****t->CDL.
3. If you are using calibre as an LVS tool, then there is a utlity
called v2lvs. The V2LVS (Verilog-to-LVS) converter translates a
Verilog structural netlist into a LVS SPICE netlist suitable for
Calibre nmLVS/nmLVS-H comparison against a layout.
Hope this help.
Riad.
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