On Aug 25, 7:43=A0am, pdw <dewit.pie...@[EMAIL PROTECTED]
> wrote:
> Hello,
> I have some standard-cell logic I want to add to an analog circuit. I
> generated the standard-cell layout using SoC Encounter and have
> im****ted it into Cadence.
>
> Is it possible to create a symbol view corresponding to the layout
> (according to the Verilog code), so I can add this symbol in my
> schematic and run a LVS for the complete system?
>
> Thanks a lot,
> Pieter
Ciao Pieter,
Yes of course it is possible.
You just need to include the cdl netlist corresponding to your digital
when running your Assura/Calibre LVS. Simple as that ;-)
Cheers,
Riad.
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