LVS on Encounter generated layout

Hello,
I have some standard-cell logic I want to add to an analog circuit. I
generated the standard-cell layout using SoC Encounter and have
im****ted it into Cadence.

Is it possible to create a symbol view corresponding to the layout
(according to the Verilog code), so I can add this symbol in my
schematic and run a LVS for the complete system?

Thanks a lot,
Pieter