I am using Verilog In to generate a schematic. However, the schematic
has all the blocks connected with wires going from pin to pin. Is
there a way that we can create a schematic with some defined wire
length coming out of each instance and just labels attached to each
net.
This way my schematic would look much cleaner (due to absence of nets
crossing each other) and still clean as everything is connected by
name.
Thanks,
Kamal
