We are UG students, presenly working with Cadence Virtuoso. After
creating a simple layout of an inverter, these are a few of the errors
which appeared in the log file when we tried running Assura DRC check
using NCSU_TechLib_ami06/divaDRC.rul.
error: Illegal input layer 'geomGetEdge(geomAndNot(elec
geomButting(elec elecHighres)))' found in drc().
error: Illegal input layer 'active' found in geomAnd().
error: Undefined layer - elecHighresEdge.
Errors exist in the rules file
'/home/chiptapeout/cadence/ncsu-cdk-1.5.1/lib/NCSU_TechLib_ami06/
divaDRC.rul'.
*WARNING* Failed to build VDB. Cannot submit DRC Run.
Assura DRC: State loaded "Last"
Could anyone please help us out?
