Thanks a lot for the reply's Stefan and Riad. It was very very
helpful.
I now understand that I could go with BSIM3 since I am using 0.13u
technology node and as you have said (also from my research during the
past 2 days).
Also I was able to find the parameter values (like k, mu, vth etc.) by
the procedure suggested by Riad. I have also made a unix search for
*.scs and *.lib files and found that some of those parameters that the
simulator has dumped come from those files infact. It would be really
interesting to know other ways of getting those parameter values.
Please Riad :-).
Also I have one more nagging question. Suppose I have two different
models for 0.13u provided by my foundry, I would like to know how can
we change the models using Cadence or someother means. Just to see the
performace of one over the other. Lets say I would like to see the
performance of one model over the other for an inverter in the
subthreshold region or in a region of transition from subthreshold to
strong inversion.
Thank you all once again,
Naveen.
On May 15, 3:55 am, Riad KACED <riad.ka...@[EMAIL PROTECTED]
> wrote:
> Dear Naveen,
>
> There are two main questions you have to ask yourself in order to find
> the best model for your application :
> 1. What is your application ? what do you want to model or simulate ?
> What is the more accurate model for your design needs ?
> You've already answered this question => MOS subthreshold region,
> which is a good start.
> 2. Is your foundry, Model or PDK provider can supply you the model you
> need ? That's im****tant as well !
>
> back to your questions :
>
> 1. BSIM3v3 is the industry standard nowadays, it has a very good
> modeling of the Sub-threshold region and it is sup****ted and provided
> by almost all the foundries.
> BSIM4 is getting more popular among the nano technologies world since
> it is solving many missing items from the BSIM3, such as the Well
> Proximity Effect (WPE), the Shallow Trench Isolation stress (STI),
> Halo/Pocket modeling, Gate direct Tunneling, GIDL ... Except these new
> silicon side effects at small geometries, i don't think BSIM4 has
> improved anything directly related to the sub-threshold region. So do
> you really need the modeling of these new stuffs ? what is your
> technology node ? If you're in 0.13u and below, I would say BSIM3 is
> fair enough.
> Apart from BSIM3, PSP has been selected as a standard for nano
> technologies by the Compact Modeling Council group, but do you really
> need it ? This is a re****t from TI about sub-Threshold modeling in
> PSP ...http://www.eigroup.org/CMC/next_gen_cmos/phase3/ti.pdf
> PSP is getting more power among the semiconductor wold but only few
> foundries are sup****ting it now ...
> Well, there are other modeling standards but my knowledge of EKV,
> HiSIM and stuff is very very weak.
> If you fancy reading about modeling, I would advice :
> 1. The CMC's (Compact Modeling Council) web
site:http://www.geia.org/index.asp?bid=597
> 2. The BSIM's web sitehttp://www-device.eecs.berkeley.edu/~bsim/
> 3. The following books:
> 3.1 Device Modeling for Analog and RF CMOS Circuit Design (Book)
> 3.2 Operation and Modeling of the MOS Transistor MOSFET
> 3.3 Models for SPICE Simulation, Including BSIM3v3 and BSIM4
>
> 2. I entirely commit with Stefan, you've to be a bit nosy ... File
> searching in Unix is not harmful. search your PDK for .scs
> (spectre), .lib (Eldo, Hspice), .gem (ADS) ...
>
> 3. These parameters are in your Spice Model Cards, and sometimes
> supplied in foundry's do***entation (few set of them).
> For your question : "But my question is where is that technology
> file", my answer is : give me the IP address of your machine, your
> username and your password, shut down all the firewalls and other
> security stuffs. I'll then log on and give you the answer. You will be
> certainly fired for this ;-) Nobody can answer this question my
> buddy ! it depends on your PDK provider. Some BAD foundries even
> change the locations from a pdk version to another ...
> Well I'm not that bad and I can say that your simulator can dump these
> parameters for you. You just need to make a test bench with one single
> transistor, biased with DC voltage sources and run a DC OP simulation.
> Go to the ADE -> Results -> Print -> Model Parameters and then select
> your MOS !! This is what I propose to begin with. There are other ways
> to do it if requested.
>
> Hope this is helping you !
>
> Riad.
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