Dear Riad,
Thank you for your quick reply.
I have generated a digital circuit, PostDiv, by Astro and LVSed it by
Calibre, using V2LVS to generate a source netlist.
Then the digital circuit's gds and .v file was im****ted into Cadence. It
has
layout view/schematic view/symbol. The digital circuit PostDiv's symbol
was
put into an existing analog cell DMP's schematic, then wired them
together.
The PostDiv's layout was put into the DMP layout. After issuing the
Calibre
lvs command, the status window said:
waiting for layout viewer to ex****t cell ...
waiting for schematic viewer to ex****t cell..
schematic ex****t filed or was cancelled. please consult the transcript in
the source window.Then it stopped.
The CIW window had the following info:
....
Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in the
view list: "auCdl schematic cmos_sch" for instance U5 in cell PostDiv.
Either add one of these views to: Library: PostDiv1 Cell: MX2X1 or modify
the view list to contain an existing view.
End netlisting May 12 22:02:07 2008
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be
corrupt
or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
mv: cannot access /ex****t/home/chenym/jingyk/gps/1/cds/lvs/si.sav
....
I have added " LVS BOX PostDiv" to LVS rule file to ignore the digital
part,
but it can not help. The above error still exist.
How I can pass the top level LVS?
Thank you in advance.
Fred.
"Riad KACED" <riad.kaced@[EMAIL PROTECTED]
>
??????:dc163706-bd69-49c2-8fd9-74aff4affa26@[EMAIL PROTECTED]
> Dear Fred,
>
> Yes of course, AMS designs are sup****ted for LVS.
> What does it mean " ... but can not do lvs when they are connected
> together in Cadence" ?
> What is the issue ? Any error messages ? Device/Connectivity/Property
> mismatch ? Or mixed up with the substrates ?
>
> Any detailed description of your problems is more than welcome ;-)
>
> Riad.
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