Ciao Andreas,
Since your problem is related to the ST PDK, I think it's working
asking your favorite CAD sup****t over there in ST. They have got very
skillful and nice chaps, I'm convinced they will be doing their best
to get this issue sorted out for you ! I can give you some names and
feel free to mention myself as reference for your request, no
worries ...
Back to your problem :
The 'short' is just a little resistance (1m Ohm by mind) which
function is to break the connectivity. One typical of using this short
is to connect a net to 2 different ****ts.
When I was designing LDOs with ST, I have used the 'short' device in
the following case : Tying the output of the amplifier to 2 separate
out pins, I can explain the purpose if needed.
Physically, your layout looks like this : ( ===== is a metal path,
let say metal1).
/==============> Out
OA =========<
\==============> Feedback
This is obviously incorrect in terms of LVS since you've shorted your
Out/Feedback ****ts. The solution is then to insert something that
makes the LVS happy, that's the 'short' device.
ST provides a CAD maker called 'mkr short' or something like this that
your draw on to of the metal path as shown here :
/==============> Out
OA =========<
\======++++====> Feedback
The ++++ is the marker in question, you can make it overlapping the
metal wire a bit.
In terms of LVS, the Feedback pin is no more connected to Out but it
is now tied to a little resistor : R(SH) r=1e-3
Having a 'short' device in schematic and this marker in layout should
make you LVS smiling !
The 'short' device has a fundamental property : Its value is fixed
(i.e 1m Ohm) regardless :
1. How 'short' is the marker in layout : If your marker is overlapping
100um of a metal length, this 100um is considered as R=1e-3. If it is
only 0.1um, it is considered the same as well.
2. On which metal level. 2 markers on different metal levels (i.e with
different resistivity) will come with the same R=1e-3.
This has been made like this just to make the life of FE designers
easier. They are just worried about putting this device in their
schematic, no matter its value ...
Well, this solution is quite good in 0.25um, 0.18um technology nodes,
but when it comes to work with the CMOS 65nm process where designers
are hunting down every single miscalculation of the wire's RC, this
solution is just baned.
So if you are working with the 65nm PDK from ST, unless it changed
since I left, the 'short' marker is no more sup****ted, you've to use
the metal resistance instead (rm1, rm2, ....). This is very annoying
since you've got any flexibility but it makes your simulations
accurate. The 'short' symbol is still available from the STLib
however. Why ? Simply because the STLib is a generic library which is
technology-independent, like the analogLib from cadence.
As far as I know, Nothing is set to make a smiley LVS with the short
device in the ST C065nm PDK.
A solution like : LVS FILTER R(SH) SOURCE SHORT won't work with the
previous test case I'm afraid (shortening two ****ts), give it a try to
confirm ...
So my conclusion is : Please contact your ST CAD sup****t, they are one
of the best sup****t teams I've ever known ;-)
Riad.
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