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Re: LVS and Shorts in Virtuoso schematics?

by Andrew Beckett <andrewb@[EMAIL PROTECTED] > Apr 30, 2008 at 11:45 AM

Andreas wrote, on 04/29/08 16:27:
> Hello,
> 
> I've got a synthesized verilog netlists containing statements, which 
> connect signals to logic high or low, e. g.
> 
> assign xy = 1'b0;    //The net xy is tied to gnd (logic low).
> 
> The problem is that I have no tiehi or tielo cells in my synthesis 
> libraries.
> 
> After im****ting the verilog netlist as a Virtuoso schematic into CDE, 
> these verilog assignments are replaced. Sometimes they're replaced by a 
> "cds_thru" cell from the "basic" library and sometimes by "short" cell 
> from the designkit. I don't understand why two different cells are used.
> 
> The real Problem occurs, when I want to do a LVS. The LVS tool tells me 
> that it can not find the "cds_thru" or "short" cells in the layout. LVS 
> results incorrect, although the layout is correct.
> 
> What can I do?
> 
> I already searched for an lvsIgnore property, but the "cds_thru" and 
> "short" cells don't have one.
> 
> Thanks for your help,
> 
> Andreas
> 

The "short" (I assume that's equivalent to the "patch" component in the
basic 
library) effectively creates an alias in the database, which says that two
net 
names are equivalent. However, aliases can only be created when one of the
nets 
is internal (i.e. if both are terminals, or both globals, or one terminal
and 
one global, it can't do it). In that case, a "cds_thru" is used. cds_thru
is 
something I proposed a few years ago to solve precisely this problem - how
to 
create a "through" connection - which is perfectly possible in Verilog,
but not 
in the CDB database. What cds_thru does is get netlisted as an assign in 
verilog, an "iprobe" (i.e. a zero-volt source) in spectre, a zero-volt
source in 
hspice, a "small" resistor in CDL (which can be filtered out in Physical 
verification tools such as Dracula, Assura and Calibre), and so on. For
Diva and 
  Assura using the auLvs view, you can add a removeDevice() call in your
LVS 
rules (I think it's filterDevice() for Assura) which shorts the device
with a 
particular name.

VirtuosoXL also knows how to treat this pseudo-device as a short.

The "patch" device shouldn't need any special handling though, as this
should be 
taken care of during netlisting - it will just map to use one of the
aliased 
names everywhere.

Regards,

Andrew.
 




 9 Posts in Topic:
LVS and Shorts in Virtuoso schematics?
Andreas <cad_group.20.  2008-04-29 17:27:38 
Re: LVS and Shorts in Virtuoso schematics?
"S. Badel" <  2008-04-29 17:32:50 
Re: LVS and Shorts in Virtuoso schematics?
Riad KACED <riad.kaced  2008-04-29 15:42:23 
Re: LVS and Shorts in Virtuoso schematics?
Andreas <cad_group.20.  2008-04-30 10:59:14 
Re: LVS and Shorts in Virtuoso schematics?
Andrew Beckett <andrew  2008-04-30 11:45:53 
Re: LVS and Shorts in Virtuoso schematics?
"S. Badel" <  2008-04-30 17:40:18 
Re: LVS and Shorts in Virtuoso schematics?
Andrew Beckett <andrew  2008-05-01 13:55:34 
Re: LVS and Shorts in Virtuoso schematics?
Riad KACED <riad.kaced  2008-04-30 17:11:48 
Re: LVS and Shorts in Virtuoso schematics?
Riad KACED <riad.kaced  2008-04-30 17:14:45 

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