Hello,
I've got a synthesized verilog netlists containing statements, which
connect signals to logic high or low, e. g.
assign xy = 1'b0; //The net xy is tied to gnd (logic low).
The problem is that I have no tiehi or tielo cells in my synthesis
libraries.
After im****ting the verilog netlist as a Virtuoso schematic into CDE,
these verilog assignments are replaced. Sometimes they're replaced by a
"cds_thru" cell from the "basic" library and sometimes by "short" cell
from the designkit. I don't understand why two different cells are used.
The real Problem occurs, when I want to do a LVS. The LVS tool tells me
that it can not find the "cds_thru" or "short" cells in the layout. LVS
results incorrect, although the layout is correct.
What can I do?
I already searched for an lvsIgnore property, but the "cds_thru" and
"short" cells don't have one.
Thanks for your help,
Andreas
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