Hi,could someone kindly help me with the simulation for Digital and Analog
circuits simutanously in Cadence enviroment,because the digital circuit
and
analog circuit have to be integrated working together . I have finished
following steps:
1. wrote verilog code and synthesized by DC and auto P&R in Astro
2. dupm verilog netlist from Astro and im****ted into cadence to generate a
schematic/symbol. Im****ted layout gds file and passed the LVS/DRC by
Calibre.
3. Added the above im****ted digital symbol view into another analog
transistor level schematic.
I use Analog Environment Spectre to simulate the digital/analog combined
circuit, but there are errors and failed to run.
Could someone kindly tell me how to configure the Analog Environment
spectre
for above simulation?
Thank you very much in advance.
Regards.
Fred
