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Computer Aided Design - CAD > Cadence > Re: Tie logic v...
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Re: Tie logic values to vdd/gnd within Encounter

by Muzaffer Kal <kal@[EMAIL PROTECTED] > Apr 2, 2008 at 05:53 PM

On Wed, 02 Apr 2008 17:13:40 +0200, Andreas
<cad_group.20.hinz@[EMAIL PROTECTED]
> wrote:
>  globalNetConnect vdd -type tiehi -module {}
>  globalNetConnect gnd -type tielo -module {}

This seems necessary but pay attention to the case of the VSS/VDD
nodes. I think they have to match the power/ground pins of your
standard cells so look at your LEF to make sure. Also you probably
don't need to module constraint there.

Also assuming you're using Nanoroute the following option should be in
your TCL file:

setNanoRouteMode -routeAllowPowerGroundPin true

Otherwise Nanoroute doesn't know what to do.
Muzaffer Kal
ASIC/FPGA Design Services
DSPIA INC.
http://www.dspia.com
 




 2 Posts in Topic:
Tie logic values to vdd/gnd within Encounter
Andreas <cad_group.20.  2008-04-02 17:13:40 
Re: Tie logic values to vdd/gnd within Encounter
Muzaffer Kal <kal@[EMA  2008-04-02 17:53:18 

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tan12V112 Wed Aug 27 23:16:23 CDT 2008.